Algoritmo de estimação de movimento e sua arquitetura de hardware para HEVC

Doutoramento em Engenharia EletrotécnicaVideo coding has been used in applications like video surveillance, video conferencing, video streaming, video broadcasting and video storage. In a typical video coding standard, many algorithms are combined to compress a video. However, one of those algorithms, the motion estimation is the most complex task. Hence, it is necessary to implement this task in real time by using appropriate VLSI architectures. This thesis proposes a new fast motion estimation algorithm and its implementation in real time. The results show that the proposed algorithm and its motion estimation hardware architecture out performs the state of the art. The proposed architecture operates at a maximum operating frequency of 241.6 MHz and is able to process 1080p@60Hz with all possible variables block sizes specified in HEVC standard as well as with motion vector search range of up to ±64 pixels.A codificação de vídeo tem sido usada em aplicações tais como, vídeovigilância, vídeo-conferência, video streaming e armazenamento de vídeo. Numa norma de codificação de vídeo, diversos algoritmos são combinados para comprimir o vídeo. Contudo, um desses algoritmos, a estimação de movimento é a tarefa mais complexa. Por isso, é necessário implementar esta tarefa em tempo real usando arquiteturas de hardware apropriadas. Esta tese propõe um algoritmo de estimação de movimento rápido bem como a sua implementação em tempo real. Os resultados mostram que o algoritmo e a arquitetura de hardware propostos têm melhor desempenho que os existentes. A arquitetura proposta opera a uma frequência máxima de 241.6 MHz e é capaz de processar imagens de resolução 1080p@60Hz, com todos os tamanhos de blocos especificados na norma HEVC, bem como um domínio de pesquisa de vetores de movimento até ±64 pixels

FPGA based synchronous multi-port SRAM architecture for motion estimation

Very often in signal and video processing applications, there is a strong demand for accessing the same memory location through multiple read ports. For video processing applications like Motion Estimation (ME), the same pixel, as part of the search window, is used in many calculations of SAD (Sum of Absolute Differences). In a design for such applications, there is a trade-off between number of effective gates used and the maximum operating frequency. Particularly, in FPGAs, the existing block RAMs do not support multiple port access and the replication of DRAM (Distributed RAM) leads to significant increase in the number of used CLBs (Configurable Logic Blocks). The present paper analyses different approaches that were previously used to solve this problem (same location reading)and proposes an effective solution by using an efficient combinational logic to synchronously and simultaneously read the video pixel memory data through multiple read-ports

Fast motion estimation algorithm for HEVC video encoder

Video compression is required in applications like video network communications, video conference, broadcasting, live streaming and video storage. H.265/HEVC is the latest video compression standard, jointly developed by JCT-VC that provides the highest compression efficiency without significant loss in original video source quality. Among all the tools in HEVC encoder, Motion Estimation (ME) is one of the most complex tasks. The present paper analyses the ME algorithm present in HEVC standard reference software and proposes two improvements to the algorithm. Our results show a decrease on the computational complexity by almost 30% with negligible loss in the video quality

Improvements to TZ search motion estimation algorithm for multiview video coding

This paper, proposes improvements to TZ search motion estimation algorithm with reference to its implementation in JMVC reference software. In TZS, the search patterns that are implemented are 8-point diamond and 8-point square. When these are replaced with hexagonal patterns, there is a large improvement in encoding time. Further, the TZS algorithm is improved by changing the searching threshold for each grid in the search area. Simulation results show that the overall encoding time can be reduced by almost 50% compared to TZS algorithm, while maintaining the same PSNR and bitrate

A novel SAD architecture for variable block size motion estimation in HEVC video coding

Motion estimation (ME) is one of the critical and most time consuming tasks in video coding. The increase of block size to 64x64 and introduction of asymmetric motion partitioning (AMP) in HEVC makes variable block size motion estimation more complex and therefore requires specific hardware architecture for real time implementation. The ME process includes the calculation of SAD (Sum of Absolute Difference) of two blocks, the current and the reference blocks. The present paper proposes low complexity SAD (Sum of Absolute Difference) architecture for ME of HEVC video encoder, which is able to exploit and optimize parallelism at various levels. The proposed architecture was implemented in FPGA, and compared with other non-parallel SAD architectures. Synthesis results show that the proposed architecture takes fewer resources in FPGA when compared with results from non-parallel architectures and other contributions

High speed SAD architectures for variable block size motion estimation in HEVC video coding

HEVC is the latest video coding standard aimed to compress double to that of its predecessor standard H.264/AVC at the cost of increased coding complexity. Motion Estimation (ME) is one of its critical tools in the encoder whose complexity drastically increases due to the increase in coding block size to 64x64 and due to the introduction of Asymmetric Motion Partitioning (AMP). Hence it requires specific hardware architectures for real time implementation. The bottleneck of ME tool is the SAD (Sum of Absolute Difference) circuit architecture which calculates SAD between current block and reference block pixels. The present paper proposes and implements three SAD architectures in FPGA. Synthesis results show that one of the proposed architectures outperforms when compared to results of other contributions, despite supporting all block modes of HEVC

Fast motion estimation algorithm for HEVC

Motion Estimation is an essential process in many video coding standards like MPEG-2, H.264/AVC and HEVC. Despite Motion Estimation has been used at the encoder, it is expected to be used in future consumer devices in the distributed video coding architectures. But the Motion Estimation itself consumes more than 50% coding complexity or time to encode. To reduce the computation time, many fast Motion Estimation Algorithms were proposed and implemented. The present paper proposes a new fast ME algorithm which outperforms the fast ME algorithm implemented in HEVC reference software HM

Complexity reduction methods for fast motion estimation in HEVC

Motion estimation is one of the most demanding and complex tools in block based video encoders. Variable block size motion estimation (ME) and multiple reference frames in H.264/AVC make motion estimation even more complex and time consuming. In HEVC, the complexity is even higher since there are more block sizes. This paper presents an analysis of various tools involved in some fast ME algorithms and proposes some improvements to them in order to achieve a novel fast hybrid algorithm. The proposed algorithm has been tested with HEVC reference software. Simulation results show that the algorithm achieves up to 44.7% decrease in ME complexity when compared to the fast ME algorithm (Test Zone Search or TZSearch) and up to 99% reduction in ME complexity compared to full search algorithm with negligible loss in PSNR and bitrate

Fast partitioning depth decision based on skipping block sizes in HEVC

High Efficiency Video Coding (HEVC) is the latest video coding standard developed under joint collaboration of ITU-T VCEG and ISO/IEC MPEG, together under the name JCT-VC (Joint Collaborative Team on Video Coding) [1-2]. Recently, in February 2013, this video coding standard was issued by ITU as H.265 and by ISO/IEC as MPEG-H Part 2. The number of possible coding block sizes (block modes), and therefore its complexity, increased in comparison to its predecessor H.264/MPEG-4 AVC. For each 64x64 pixel coding unit (CU), there are 1361 CU partitions. In the encoding process, very few CU partitions are selected. In this paper, we avoid the calculation of most likely unselected CU partitions in Inter coding. Using TZ motion estimation algorithm, our fast partitioning depth decision mode algorithm saves 17% of the complexity, with negligible loss in PSNR and bit rate, in comparison to algorithm implemented in HEVC test model (HM) 10.0 encode